Methodology on developing metal fill as library device and design structure
US8640076B2 · kind B2 · utility
1Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2010 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Mar 22, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A methodology is provided on developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.