Thin film transistor having a patterned passivation layer

US8643006B2 · kind B2 · utility

Assignee

• Au Optronics Corporation · TW

Inventors

• Chia-Hsiang Chen · Sunnyvale, US
• Ming-Chin Hung · Cupertino, US
• Chun-Hao Tu · 埔鹽鄉, TW
• Wei-Ting Lin
• Jiun-Jye Chang · Cupertino, US

Key dates

• Filing date: Jun 20, 2011
• Grant date: Feb 4, 2014
• Expiry date: Sep 27, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6755

Abstract

A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a gate insulating layer, a source and a drain, a channel layer, and first and second patterned passivation layers. The gate is disposed on the substrate. The gate insulating layer is disposed on the gate. The source and the drain are disposed on the gate insulating layer. The channel layer is disposed above or under the source and the drain, wherein a portion of the channel layer is exposed between the source and the drain. The first patterned passivation layer is disposed on the portion of the channel layer, wherein the first patterned passivation layer includes metal oxide, and the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms. The second patterned passivation layer covers the first patterned passivation layer, the gate insulating layer, and the source and the drain.