On-chip interconnects VIAS and method of fabrication
US8643187B1 · kind B1 · utility
1Cited by
3References
19Claims
0Family size
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Key dates
| Filing date | Jun 1, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Jun 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnection system is provided with reduced capacitance between a signal via and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric constant of the system is reduced. The signal vias are surrounded with some combination of open trenches and/or grounded vias to decrease the effective dielectric constant of the surrounding system, providing shielding from the interference of nearby signal lines and vias. The fabrication techniques provided are advantageous because they can be preformed using today's standard IC fabrication techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.