Asymmetric signal routing in a programmable logic device
US8643399B1 · kind B1 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Sep 9, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Sep 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes an array of functional blocks and input/output elements disposed at the periphery of the programmable logic device. The programmable logic device also includes conductors configured to conduct signals between the functional blocks and between the functional blocks and the routing channels. The number of conductors that propagate signals in a direction toward the periphery and out of the array is greater than the number of conductors that propagate signals into the array in a direction away from the periphery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.