Feed-forward analog-to-digital converter (ADC) with a reduced number of amplifiers and feed-forward signal paths
US8643524B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2012 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Oct 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/474
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) having a reduced number of amplifiers and feed-forward signal paths provides for reduced complexity and power consumption. The analog-to-digital converter includes a delta-sigma modulator having a loop filter with second-order stages implemented with a single amplifier each, provided by a series-connected capacitive feedback network with a switched capacitor shunt. The reduction in the amplifier stages reduces the number of inputs to, and dynamic range required from, the summing node that provides input to the quantizer, as well as reducing the power requirements and complexity of the circuit due to the reduced number of amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.