PFC with high efficiency at low load
US8644041B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2010 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Jul 8, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A Power Factor Corrector (PFC), typically used as the first stage of switched mode power supplies, particularly suited for Universal Mains inputs, is disclosed, along with methods for controlling a switched mode power supply having power factor correction. In order to increase efficiency, particularly under low load conditions, without undue degradation of the Power Factor, the switching of the PFC circuit is confined to one or more operating windows within each half-cycle. In example embodiments, the operating window comprises a small time window centered around the peak of the mains voltage. The higher the power level, the wider the switching window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.