Multi-level memory device using resistance material
US8644062B2 · kind B2 · utility
2Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2010 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Oct 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same pulse height and different pulse widths are applied to the MLC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.