Scaleable look-up table based memory
US8644100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Nov 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.