Mechanism for an efficient DLL training protocol during a frequency change
US8645743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2010 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Jun 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.