Cable redundancy and failover for multi-lane PCI express IO interconnections
US8645746B2 · kind B2 · utility
5Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2010 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Mar 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.