Determining page faulting behavior of a memory operation
US8645758B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Apr 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to page faulting of memory operations in a subject code block. An aspect of the invention concerns an apparatus comprising a component for identifying a first object node having a first dependency path and second object node having a second dependency path, and a component for calculating a numerical difference between a first addressing value and a second addressing value, where the first and second addressing values are respectively associated with the first and second dependency paths. The apparatus may include a dependency generator for ordering a subject order list of the subject code block in an object dependency non-page-faulting order when the numerical difference is equal to or less than an assigned memory page size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.