Method for controlling a basic parity node of a non-binary LDPC code decoder, and corresponding basic parity node processor
US8645787B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 5, 2010 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Jul 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U1, U2) having nm elements sorted in ascending or descending order, nm being greater than 1, and gives an output list (Uout) of nm′ elements sorted in said ascending or descending order, nm′ being greater than 1, each element of the output list (Uout) being the result of a computing operation φ between an element of the first input list (U1) and an element of the second input list (U2). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.