System and method for selective error checking
US8645811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Apr 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.