Methodology for performing post layer generation check
US8645876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Sep 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.