Patent · US Active

Checking an ESD behavior of integrated circuits on the circuit level

US8645895B2 · kind B2 · utility

6Cited by

4References

20Claims

0Family size

Assignee

X-FAB SEMICONDUCTOR FOUNDRIES GMBH · DE

Inventors

Lars Bergmann · Waiblingen, DE
Angela Konrad · Erfurt, DE
Markus Frank · Baden-Baden, DE

Key dates

Filing date	Dec 4, 2008
Grant date	Feb 4, 2014
Priority date	—
Expiry date	Sep 14, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/601
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and a method for testing the ESD behavior, wherein a circuit (7) is automatically tested at circuit diagram level in that technology-specific ESD data is provided in database (2) for each circuit component present in the circuit, without requiring complex circuit simulations, for example based on front end or back end data, by taking into account the layout.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.