Semiconductor integrated circuit

US8648392B2 · kind B2 · utility

Assignee

• PANASONIC HOLDINGS CORPORATION · JP

Inventors

• Hidetoshi Nishimura · Osaka, JP
• Masaki Tamaru · Kyoto, JP

Key dates

• Filing date: Nov 16, 2010
• Grant date: Feb 11, 2014
• Expiry date: Dec 26, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/907

Abstract

A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines.