Apparatus and methods for controlled error injection
US8650447B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2011 |
| Grant date | Feb 11, 2014 |
| Priority date | — |
| Expiry date | May 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment of the invention, precision control of error injection may be accomplished by way of synchronous error signals accompanying data transfers along various pipeline stages of a data path. The synchronous error signals may be used to trigger error events in a given protocol logic block (i.e. in a given sub-component of the data path). The protocol logic block is configurable to determine whether any action is to be taken upon the assertion of the error signal. Multiple error events may be triggered as the data signal (and its accompanying synchronous error signal) passes through pipelined functions of the data path so as to create complex error conditions. In addition, deterministic handling of created errors may be accomplished using a loopback path with bypassable blocks on both forward and reverse transformations. Other embodiments, aspects and features are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.