Memory device, memory system, and authentication method
US8650654B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2011 |
| Grant date | Feb 11, 2014 |
| Priority date | — |
| Expiry date | Mar 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/2516
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory device includes a third partial key write module, an encryption key write module, and a decryption module. The third partial key write module is configured to combine a second partial key received from the current host device with the first partial key in the partial key memory device and to write a generated third partial key into the volatile memory after the device authentication. The encryption key write module is configured to combine the third partial key with the second user authentication information and to write a generated encryption key into the volatile memory after the user authentication. The decryption module is configured to decrypt the encrypted data based on the encryption key in the volatile memory based on a read request received from the current host device and to output obtained data to the current host device when the user authentication has succeeded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.