Chip testing method
US8652858B2 · kind B2 · utility
1Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2012 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Apr 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip testing method includes cutting a wafer into chip packages, re-arranging the chip packages on a chip tray, and testing the re-arranged chip packages. The wafer includes a plurality of substrates vertically stacked thereon, and each of the plurality of substrates has a plurality of chips mounted thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.