Multichip packaging for imaging system
US8653467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2012 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jul 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73267
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A receiver chip for use in an imaging system includes a plurality of receiver dies, each of the receiver dies comprising one or more receiver circuits; a die interconnection layer located on top of the plurality of receiver dies; a quarter wave dielectric layer located on top of the die interconnection layer; and a plurality of antennae located on the quarter wave dielectric layer, each of the plurality of antennae corresponding to a respective receiver circuit, wherein the plurality of antennae are connected to the one or more receiver circuits through the quarter wave dielectric layer and the die interconnection layer by respective vias, such that a distance between a topmost layer of the die interconnection layer and the plurality of antennae is determined by a thickness of the quarter wave dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.