Electronic device and method for buffering
US8653856B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jul 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.