Clock gated power saving shift register
US8654226B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2011 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jan 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gated-clock shift register including a series of clocked flip-flops with preceding outputs connected to subsequent inputs as a horizontal digital shift register. Each flip-flop (or other state holding device) includes a clock buffer between the respective flip-flop's clock, and the global clock. Each clock buffer propagates the clock signal when it determines the associated flip-flop will have a state change during that clock cycle (e.g., via an XOR of the flip-flops input and output signals). In the absence of a state change, that buffer does not propagate the clock signal, essentially only clocking the relevant flip-flops. Further, the clock buffer may be implemented with only NMOS devices (or alternatively, only PMOS devices), which offers power savings over an otherwise required CMOS implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.