High voltage electrostatic discharge clamp using deep submicron CMOS technology
US8654490B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2012 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Apr 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.