Modeling loading effects of a transistor network
US8655634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2010 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jul 8, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.