Dual ported replicated data cache
US8656214B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | May 24, 2010 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Apr 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.