Patent · US Active

System on chip breakpoint methodology

US8656221B2 · kind B2 · utility

32Cited by

9References

16Claims

0Family size

Assignee

Mobileye Technologies Limited · CY

Inventors

Emmanuel Sixsou · Jerusalem, IL
Elchanan Rushinek · Petah Tikva, IL
Mois Navon · Beer Sheva, IL

Key dates

Filing date	May 13, 2010
Grant date	Feb 18, 2014
Priority date	—
Expiry date	Jun 17, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/362
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured to program the computing elements with task descriptors and the computing elements are configured to receive the task descriptors and to perform a computation based on the task descriptors. The task descriptors include a field which specifies a breakpoint state of the computing element. A system level event status register (ESR) attaches to and is accessible by the CPU and the computing elements. Each of the computing elements has a comparator configured to compare the present state of the computing element to the breakpoint state. The computing element is configured to drive a breakpoint event to the event status register (ESR) if the present state of the computing element is the breakpoint state. Each of the computing elements has a halt logic unit operatively attached thereto, wherein the halt logic unit is configured to halt operation of the computing element. The ESR is configurable to drive a breakpoint event to the halt logic units to halt at least one of the computing elements other…

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.