Method of fabricating an integrated circuit device having backside bevel protection
US8658483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Dec 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit device is provided. The method includes forming a replacement gate structure with a dummy polysilicon layer on a first surface of a substrate. The method further includes depositing a dielectric layer by a thermal process to form offset spacers on two opposing sides of the replacement gate structure, wherein the dielectric layer is deposited on the first surface and a second surface opposing the first surface of the substrate. The method further includes removing the dummy polysilicon layer from the replacement gate structure, wherein the dielectric layer on the second surface of the substrate protects the second surface of the substrate during the removing step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.