Multi-chip package and manufacturing method
US8659134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2009 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Mar 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Manufacturing method and a multi-chip package, which comprises a conductor pattern (1) and insulation (2), and, inside the insulation, a first component (3), the contact terminals (4) of which face towards the conductor pattern (1) and are conductively connected to the conductor pattern (1). The multi-chip package also comprises inside the insulation (2) a second semiconductor chip (13), the contact terminals (14) of which face towards the same conductor pattern (1) and are conductively connected through contact elements (15) to this conductor pattern (1). The semiconductor chips are located in such a way that the first semiconductor chip (3) is located between the second semiconductor chip (13) and the conductor pattern (1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.