Patent · US Active

Stacked semiconductor device and manufacturing method thereof

US8659137B2 · kind B2 · utility

3Cited by
7References
7Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 20, 2013
Grant dateFeb 25, 2014
Priority date—
Expiry dateAug 20, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/181
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.