Die structure, manufacturing method and substrate thereof
US8659160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2011 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Sep 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8582
Abstract
A die structure, a manufacturing method and a substrate, wherein the die structure is constituted by a chip on wafer (COW) and the substrate, and the substrate is formed by stacking and then cutting a plurality of thermal and electrical conductive poles and a plurality of insulating material layers. Moreover, the fabricating of the die structure comprises a plurality of COWs carried on a carrier board is bonded on the substrate, the plurality of COWs are in contact with the plurality of thermal and electrical conductive poles on the substrate, and then the carrier board is removed. After that, a phosphor plate is adhered on the plurality of COWs so as to form a stacked structure. Thereafter, the stacked structure is cut, thus forming a plurality of die structures having at least one COW.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.