Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation

US8659362B2 · kind B2 · utility

Assignee

• Cadence AMS Design India Private Limited · IN

Inventors

• Prasenjit Bhowmik · Bengaluru, IN
• Rishi Mathur · Delhi, IN
• Sriram Ganesan · North Wales, US
• Sunil Rajan · Bengaluru, IN

Key dates

• Filing date: Nov 22, 2011
• Grant date: Feb 25, 2014
• Expiry date: Nov 22, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K3/0231
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.