Analog to digital converter circuit
US8659461B1 · kind B1 · utility
19Cited by
1References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Nov 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) circuit with decoupled flip-around MDAC, capacitive attenuation solution and self-embedded offset cancellation. The flip-around MDAC architecture is built for low inter-stage gain implementation. A capacitive attenuation solution is provided for minimizing the power dissipation and optimizing conversion speed. The design reuses SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.