Analog-digital converter and converting method using clock delay
US8659464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Aug 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present inventive concept relates to an analog-digital converter. The analog-digital converter includes a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal according to a control signal; a capacitive digital-analog converting unit outputting a difference between the analog signal and a reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.