Multi-chip antenna diversity picture-in-picture architecture
US8659706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2013 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | May 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/6112
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.