Advanced memory device having improved performance, reduced power and increased reliability
US8659959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Aug 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.