Adaptive read wordline voltage boosting apparatus and method for multi-port SRAM
US8659972B2 · kind B2 · utility
9Cited by
7References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Jul 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.