Reduced frequency data processing using a matched filter set front end
US8660220B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2008 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Dec 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03248
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present invention provide systems and methods for reduced clock rate data processing. As an example, a circuit is disclosed that includes a matched filter bank that receives a series of symbols at a rate corresponding to a sample clock. The matched filter bank includes a first matched filter tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and a second matched filter tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence. The circuit further includes a detector circuit that processes a series of symbol proxies including the first symbol proxy and the second symbol proxy at a rate corresponding to a reduced rate clock. The reduced rate clock is the sample clock divided by a factor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.