Channel controller for multi-channel cache
US8661200B2 · kind B2 · utility
2Cited by
5References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2010 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Jun 5, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a channel controller for a multi-channel cache memory, and a method that includes receiving a memory address associated with a memory access request to a main memory of a data processing system; translating the memory address to form a first access portion identifying at least one partition of a multi-channel cache memory, and at least one further access portion, where the at least one partition includes at least one channel; and applying the at least one further access portion to the at least one channel of the multi-channel cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.