Modeling for soft error specification
US8661382B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2009 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Jul 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Soft error modeling of circuits. Soft error upset (SEU) specification and design information is received from a design entry. The SEU specification comprises expected SEU behavior of a node. A logical simulation model is created based on the SEU specification and the design information. A logical verification is performed based on the logical simulation model to produce a first result. The logical verification comprises selecting a first node for injection, injecting an SEU into the first node to produce a first result, and responsive to the first result not agreeing with the SEU specification, providing the first result to the design entry. A netlist based on the SEU specification and the design information is created. The netlist comprises a specification-based-logic-derating derived from the SEU specification. A physical design verification based on the netlist, a logic derating, and clock information is performed. It comprises calculating node failure-in-time based on the specification-based-logic-derating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.