Method and apparatus for performing delay annotation
US8661385B1 · kind B1 · utility
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31Claims
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Key dates
| Filing date | Sep 7, 2007 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Dec 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device includes performing delay annotation where a first delay associated with a first aspect of the system is determined by a first software thread and a second delay associated with a second aspect of the system is determined by a second software thread and the first and second software threads operate in parallel. Ensuring independence between each aspect of the system will facilitate efficient parallelism (i.e. minimal synchronization) while still maintaining serial equivalency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.