Method of packing-based macro placement and semiconductor chip using the same
US8661388B2 · kind B2 · utility
7Cited by
12References
13Claims
0Family size
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Key dates
| Filing date | Oct 1, 2009 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Feb 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.