Depth-optimal mapping of logic chains in reconfigurable fabrics
US8661394B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2008 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Jan 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of creating logic chains in a Boolean network of a reconfigurable fabric is provided. The method includes creating a plurality of logic chains in the reconfigurable fabric. The plurality of logic chains include at least one arithmetic logic chain and at least one non-arithmetic logic chain. A method of creating logic chains in a Boolean network of a look-up table based FPGA includes: applying a labeling method by (a) finding a depth increasing node, (b) isolating the depth increasing node, and (c) finding minimum height cuts; mapping to generate a mapping solution using the minimum height cuts; applying a duplication method to implement an exclusivity constraint; and arranging connections in the look-up table based FPGA using the logic chains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.