Method for dummy metal and dummy via insertion
US8661395B2 · kind B2 · utility
2Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Oct 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.