Multiple mold structure methods of manufacturing vertical memory devices
US8664101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2012 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Sep 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.