Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package
US8664762B2 · kind B2 · utility
0Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2012 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Aug 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.