Patent · US Active

Dead-time generating circuit and motor control apparatus

US8665003B2 · kind B2 · utility

1Cited by
0References
4Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 3, 2010
Grant dateMar 4, 2014
Priority date
Expiry dateSep 28, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K17/16
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.