Controlling a MOS transistor
US8665004B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 4, 2007 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Jun 8, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device for controlling (10) a power transistor (5), comprises: an amplifying device (15) for monitoring the transistor gate (5) via an output control signal, the device including: a first input connected to the transistor drain, the whole assembly forming a first circuit portion; a second input connected to the transistor source, the whole assembly forming a second circuit portion. The control device comprises means for producing a polarizing current (I1, I2), the current being injected into the first and second inputs (NEG, POS) so as to offset the drain-source voltage measurement and maintain a linear operating mode of the output control signal, prior to opening the transistor, and the same number of N semiconductor junctions in the first and second circuit portions. The device is applicable in particular on battery charging devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.