Circuit and method for sub-harmonic elimination of a power converter
US8665010B2 · kind B2 · utility
2Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | May 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/12
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit and method are provided for a power converter to select one from a plurality of current limit signals as a final current limit signal according to the present duty ratio of a power switch for the pulse width modulation of the next cycle, so that the duty ratio of the power switch in the next cycle is prevented from acute variation to eliminate sub-harmonic which otherwise may happen.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.