T-type three-level inverter circuit
US8665619B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Sep 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/34
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
This invention relates to a T-type three-level inverter circuit. The circuit includes an absorption unit. In the absorption unit, a first terminal of the first resistor is connected to a positive bus terminal, and a second terminal of the first resistor is connected to a first terminal of the first capacitor and a negative electrode of the first diode; a second terminal of the first capacitor and an positive electrode of the first diode are respectively connected to an emitter and a collector of the first controllable switch tube; a first terminal of the second resistor is connected to a negative bus terminal, and a second terminal of the second resistor is connected to a positive electrode of a third diode; a negative electrode of the third diode is connected to both a first terminal of the second capacitor and a positive electrode of a second diode; and a second terminal of the second capacitor and a negative electrode of the second diode are respectively connected to a collector and a emitter of the second controllable switch tube. As the T-type three-level inverter circuit according to the invention is implemented, a voltage stress on the bidirectional switch tube is effectivel…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.