Embedded end-to-end delay information for data networks
US8665884B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 25, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Apr 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/0858
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system comprises a plurality of nodes, at least one of the plurality of nodes configured to insert, on a per-virtual link basis, a delay value into a dynamic delay field of a frame corresponding to the respective virtual link, wherein the dynamic delay value represents latency of frames of the respective virtual link. The system also comprises a switch having a plurality of ports, each port coupled to one of the plurality of nodes. The switch is configured to route frames received from the plurality of nodes to one or more of the plurality of nodes. At least one of the plurality of nodes is configured to store frames received from the switch in a buffer and to update the value in the dynamic delay field to reflect the end-to-end system delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.